Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 85)

Functional Description
ATCA-7480 Installation and Use (6806800T17A) 85
4.4 Platform Controller Hub (PCH) Intel C612
Wellsburg
The Next Generation Communications Platform Controller hub (codename Wellsburg) Intel
C612 PCH provides access between processors and the I/O subsystem. The PCH connects to
CPU#0 through Intel DMI2.0, PCH I/O-controller connected to DMI2 interface of CPU#0.
ATCA-7480 supports Intel Hybrid Clocking Mode through the Intel C612 PCH controller. By
default, Spread Spectrum Clocking (SSC) feature is enabled for the 100MHz CPU and the PCIe
clocks, which are provided by the Intel C612 and buffered through DB1900 buffer. If SSC is
enabled in BIOS settings, all PCIe devices that are connected on-board or via RTM module will
receive SSC clock. SSC can be disabled using BIOS settings.
The SSC tolerance is +/-0.25% from nominal frequency (100 MHz).
4.4.1 PCH I/O Controller Features
PCH I/O Controller features:
 X4 PCIe Gen1 (2.5GT/s) connected to VGA module slot
 8237 DMA controller
 8254 based Counter Timer/timers
 8259 Interrupt Controllers PIC (D31:F0)
 I/O APIC controller (D31:F0)
 Serial Interrupt (D31:F0)
 RTC with 256-byte battery-backed SRAM (D31:F0) (D31:F7)
 Processor Interface (D31:F0) including Thermtrip input and A20GATE, INIT3_3V,
CPUPWRGD, PMSYNC#, PECI
 Two stage Watchdog timer (WDT) (D31:F7)
 SPI Interface (Boot Flash)
 LPC/KCS Interface
 Up to 10 serial ATA (SATA) controllers 6Gb/s of which four are used on ATCA-7480
 Six USB 3.0 and 8 PCIe 2.0 interfaces of which 2+2 are used on ATCA-7480