Artesyn ATCA-7480 Installation and Use (February 2015) - Manual (Page 128)

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A) 128
1
For LPC I/O address 0x80 is used. See Table 5-5 POST Code Register.
0x62 r/w1c - Telecom Clock Monitor Out of Range Register (See,
Table 5-92 )
0x63 r/w - Telecom Clock Monitor Select Register (See, Table
5-93 )
0x64 r/w - Telecom Clock Monitor Time Base Register (See, Table
5-94 )
0x66-0x67 r/w - Telecom Clock Monitor Frequency/Period Register
(See,
Table 5-95 )
0x68-0x69 r/w - Telecom Clock Monitor Lower Limit Register (See,
Table 5-96 )
0x6A-0x6B r/w - Telecom Clock Monitor Upper Limit Register (See,
Table 5-97 )
0x74 r/w r BIOS Version Register 1 (See, Table 5-98 )
0x75 r/w r BIOS Version Register 2 (See, Table 5-99 )
0x76 r/w r BIOS Version Register 3 (See, Table 5-100 )
0x78 r r/w IPMC BIOS Communication Register 1 (See, Table
5-101 )
0x79 r r/w IPMC BIOS Communication Register 2 (See, Table
5-102 )
0x7A r r/w IPMC BIOS Communication Register 3 (See, Table
5-103 )
0x7D r/w r LPC Scratch Register (See, Table 5-104 )
0x7E r r/w IPMC Scratch Register (See, Table 5-105 )
0x7F 1 r/w r POST Code Register (See, Table 5-5 )
Table 5-38 FPGA Register Map Overview (continued)
LPC Address Offset LPC I/O IPMC I2C Description