GW Instek PEL-2000 Series Programming User Manual - Manual (Page 169)

STATUS REGISTERS
169
CME The Command Error bit is set when a
syntax error has occurred. The CME bit
can also be set when a command
is received within a program message.
(Group Execute Trigger) as defined in
IEEE 488.1.
Event Register The Event Register will be set to 0 when read.
Enable Register The Enable Register determines which events will
set the ESB Bit (bit 5) in the Status Byte Register.
Status Byte Register
Description The Status Byte register consolidates the status
events of all the status registers. The Status Byte
register can be read with the *STB? query or a
serial poll and can be cleared with the *CLS
command.
Status Byte Register
8
3
4
2
2
1
1
0
QUES CSUM 0 0
128
7
64
6
32
5
16
4
0 MSS ESB MAV
Bit weight
Bit Position
Condition
Status Bits CSUM The CSUM bit is set when an Enabled
event has occurred on a channel. The
Channel Condition, Channel Event and
Channel Summary Event Registers all
determine if the CSUM bit is set.
QUES The Questionable bit is set when a
questionable event has occurred.
MAV The Message Available bit is set when
there is outstanding data in the Output
Queue.
ESB The Event Status bit is set if an enabled
event in the Standard Event Status Event
Register has occurred.