Toshiba H1 Series - Manual (Page 542)

TMP92CZ26A
92CZ26A-539
When LCDCTL0=1 and LCDCTL0=1, frame output is inverted at
intervals set in LCDDVM0 and the LFR signal is inverted at intervals of
“LCP0 × M”. The “M” value is specified in LCDDVM0.
When ="1" LFR signal synchronous with front edge of LHSYNC signal.
So, prohibit to set =1, always need to set =0.
LVSYNC
LHSYNC
LHSYNC (Expansion)
LCP0
M M
N
LFR
=0
= 1
= N
= M
= 1
Note prohibit to set =1, always need to set =0.