Toshiba H1 Series - Manual (Page 150)

TMP92CZ26A
92CZ26A-147
Port J register
7 6 5 4 3 2 1 0
bit Symbol PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
Read/Write R/W
After reset
1 Data from external port
(Output latch register is
set to “1”)
1 1 1 1 1
Port J control register
7 6 5 4 3 2 1 0
bit Symbol PJ6C PJ5C
Read/Write W
After reset 0 0
Function 0: Input, 1: Output
Port J function register
7 6 5 4 3 2 1 0
bit Symbol PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F
Read/Write W
After
reset 0 0 0 0 0 0 0 0
Function
0: Port
1: SDCKE 0: Port
1: NDCLE 0: Port
1: NDALE 0: Port
1:
SDLUDQM
0: Port
1:
SDLLDQM
0: Port
1: SDWE ,
SRWR
0: Port
1: SDCAS ,
SRLUB
0: Port
1: SDRAS,
SRLLB
Port J drive register
7 6 5 4 3 2 1 0
bit Symbol PJ7D PJ6D PJ5D PJ4D PJ3D PJ2D PJ1D PJ0D
Read/Write R/W
After reset 1 1 1 1 1 1 1 1
Function Input/Output buffer drive register for standby mode
Note 1: Read-Modify-Write is prohibited for the registers PJCR and PJFC.
Figure 3.7.33 Register for Port J
PJ
(004CH)
PJFC
(004FH)
PJCR
(004EH)
PJDR
(0093H)