Toshiba H1 Series User Manual
Page 253

TMP92CZ26A
92CZ26A-250
This bit is used to enable or disable the interrupt to be generated when the calculation of
error address and error bit position has ended.
The interrupt is enabled when this bit is set to “1” and disabled when “0”.
(e)
The
This bit is used to enable or disable the interrupt to be generated when the status of the
NDR/B pin of the NAND Flash changes from “busy” (0) to “ready” (1). The interrupt is
enabled when this bit is set to “1” and disabled when “0”.
(f)
The
Hamming codes, they have no meaning.
These bits are used as flags to indicate the result of error address and error bit
calculation. For details, see Table 3.11.2.