Toshiba H1 Series - Manual (Page 274)

TMP92CZ26A
92CZ26A-271
3.12.2 Operation of Each Circuit
(1) Prescaler
A 9-bit prescaler generates the input clock to TMRA01.The clock φT0 is selected
using the prescaler clock selection register SYSCR0.
The prescaler operation can be controlled using TA01RUN in the timer
control register. Setting to 1 starts the count; setting to 0
clears the prescaler to 0 and stops operation. Table shows the various prescaler output
clock resolutions.
(Although the prescaler and the timer counter can be started separately, the timer
counter’s operation depends on the prescaler’s input timing.)
Table 3.12.2 Prescaler Output Clock Resolution
Timer counter input clock
Prescaler of TMRA
TAxxMOD
Clock gear
selection
SYSCR1
Prescaler of
clock gear
SYSCR0
−
φT1(1/2) φT4(1/8) φT16(1/32) φT256(1/512)
000(1/1) fc/8 fc/32 fc/128 fc/2048
001(1/2) fc/16 fc/64 fc/256 fc/4096
010(1/4) fc/32 fc/128 fc/512 fc/8192
011(1/8) fc/64 fc/256 fc/1024 fc/16384
100(1/16)
0(1/2)
fc/128 fc/512 fc/2048 fc/32768
000(1/1) fc/32 fc/128 fc/512 fc/8192
001(1/2) fc/64 fc/256 fc/1024 fc/16384
010(1/4) fc/128 fc/512 fc/2048 fc/32768
011(1/8) fc/256 fc/1024 fc/4096 fc/65536
fc
100(1/16)
1(1/8)
1/2
fc/512 fc/2048 fc/8192 fc/131072
(2) Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits TA01RUN
and TA01RUN can be used to stop and clear the up counters
and to control their count. A reset clears both up counters, stopping the timers.
Note: TMR45 and TMR67 can select low-frequency clock(fs) instead of external clock input.