Toshiba H1 Series - Manual (Page 270)

TMP92CZ26A
92CZ26A-267
3.12.1 Block Diagram
Figure 3.12.1 TMRA01 Block Diagram
φT1
φT16
φT256
8-bit comparato
r
(CP1)
8-bit up counter
(CP0)
8-bit up counter
(UC0)
2
n
Ov
er
flow
8-bit up counter
(UC1)
Ti
mer
flip-
flop
TA1FF
Match detect
Match detect
8-bit timer
register
TA1REG
φT1 φT4
φT16
512
256
128
64
32
16
8
4
2 φT1
φT4
φT16
φT256
Run/clea
r
Pr
escale
r
TA01MOD
Pr
escale
r
clock φT0
TMR
TA01RUN<
TA0
RUN>
Selecto
r
8-bit timer regist
er
TA0REG
TA01MOD
TA01MOD
TMRA0 Interrup
t output:
INTTA0
TMRA0 Interrup
t output:
TA0TR
G
TA01MOD
TA01RUN<
TA1
RUN>
TA1FF
CR
Ti
mer fl
ip
-fl
op
output: TA1
O
UT
TMRA1 Interrup
t output:
INTTA1
Internaldata bus
TA01RUN
TA01RUN
Selecto
r
Internal data bus
T
A
0TRG
Register buffer 0
External input
clock: T
A0IN