Toshiba H1 Series - Manual (Page 532)

TMP92CZ26A
92CZ26A-529
The enable width of the LHSYNC signal is set using LCDHSW. It can be
specified in a range of 1 to 512 pulses of the LCP0 clock.
The enable width is represented by the following equation:
Enable
width = + 1
Thus, when LCDHSW is set to “0”, the enable width is set as one pulse of
the LCP0 clock.
LCDHSW Register
7 6 5 4 3 2 1 0
bit Symbol HSW7 HSW6 HSW5 HSW4 HSW3 HSW2 HSW1 HSW0
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function LHSYNC width (bits 7-0)
7 6 5 4 3 2 1 0
bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8
Read/Write W
After reset 0 0 0 0 0 0 0 0
Function
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8) LGOE0
width (bit 8)
LLOAD width (bits 9-8) LHSYNC
width (bit 8)
LCP0
Signal Name
LHSYNC signal
High width setting
LCP0 clock = 1, 2, 3 … 512 pulses
LCDHSW
(0294H)
LCDHWB8
(0299H)