Toshiba H1 Series User Manual
Page 510

TMP92CZ26A
92CZ26A-507
immediately. At the same time, the read and write pointers of the FIFO, the data in
the output shift register and the clock generator are all cleared. (However, when
I2SnCTL
I2SnCTL
resumed, no data will be output.
The WS signal stops at Low level and the CK signal stops at Low level when the
rising edge is selected and at High level when the falling edge is selected.
3) I2SnCTL
I2SnCTL
counter) for generating the I2SnCKO and I2SnWSOsignals.
Setting I2SnCTL
stops the counters. Normally, I
2
S data transmission is executed by setting both
I2SnCTL
I2SnCTL
To clear the clock generator, I2SnCTL
4) FIFO buffer
The I
2
S unit is provided with a 128-byte FIFO. Although it is not necessary to use all
128 bytes in the FIFO, data should basically be written in units of 64 bytes using an
INTI2Sn interrupt as a trigger. If data is written to the FIFO without waiting for an
INTI2Sn interrupt or in units other than 64 bytes, interrupts cannot be generated
properly.
If the last set of data, for which an interrupt is not needed, contains less than 64
bytes, set I2SnCTL
checking that the
after all the data has been transmitted). In case monaural setting, make sure that the
FIFO is empty by checking the I2SnCTL
periods of the I2SWS signal (after all the data has been transmitted), set
“0”.
5) I2SnBUF
When writing data to the I2SnBUF register, be sure to use long-word data load
instructions. Word data load or byte data load instructions cannot be used.
Examples)
ld
(I2SnBUF), xwa;
OK
ld (I2SnBUF),
wa; NG
ld (I2SnBUF),
a; NG