Toshiba H1 Series User Manual
Page 250

TMP92CZ26A
92CZ26A-247
(c)
The
This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC
generator (to set
(d)
The
codes to control the pins of the NAND Flash memory.
(e)
The
write operations.
(f)
The
this bit should be set to “0”.
Since valid data and ECC are processed differently, the NDFC needs to know whether
valid data or ECC is to be read. This control is implemented by software using this bit.
To read valid data from the NAND Flash, set
the redundant area in the NAND Flash, set
Note 1: Valid data and ECC cannot be read continuously by DMA transfer. After valid data has been read, DMA
transfer should be stopped once to change the
Note 2: Immediately after ECC is read from the NAND Flash, the NAND Flash access operation or error bit
calculation cannot be performed for a duration of 20 system clocks (f
SYS
). It is necessary to insert 20 NOP
instructions or the like.
(g)
The
The error address and error bit position are calculated using an intermediate code
generated from the ECC for written data and the ECC for read data. Setting
“1” starts this calculation.
(h)
The
bit should be set to “0”.
For a write operation, this bit should be set to “0” (encode) to generate ECC. The ECC
read from the NDECCRDn register is written to the redundant area in the NAND Flash.
For a read operation, this bit should be set to “1” (decode). In this case, valid data is read
from the NAND Flash and the ECC written in the redundant area is also read to generate
an intermediate code for calculating the error address and error bit position.