Toshiba H1 Series - Manual (Page 356)

TMP92CZ26A
92CZ26A-353
(6) Transmitter/Receiver selection
Set the SBICR2 to “1” for operating the TMP92CZ26A as a transmitter.
Clear the to “0” for operation as a receiver.
In Slave Mode,
z Data with an addressing format is transferred
z A slave address with the same value that an I2CAR
z A GENERAL CALL is received (all 8-bit data are “0” after a start condition)
The is set to “1” by the hardware if the direction bit ( W R/ ) sent from the
master device is “1”, and is cleared to “0” by the hardware if the bit is “0”.
In the Master Mode, after an Acknowledge signal is returned from the slave device,
the is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is
set to “1” by the hardware if it is “0”. When an Acknowledge signal is not returned, the
current condition is maintained.
The is cleared to “0” by the hardware after a stop condition on the I
2 C bus is
detected or arbitration is lost.
(7) Start/Stop condition generation
When the SBISR is “0”, slave address and direction bit which are set to
SBIDBR are output on a bus after generating a start condition by writing “1” to the
SBICR2 . It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set “1” to beforehand.
Figure 3.15.10 Start condition generation and slave address generation
When the is “1”, a sequence of generating a stop condition is started by
writing “1” to the , and “0” to the . Do not modify the contents
of until a stop condition is generated on a bus.
Figure 3.15.11 Stop condition generation
The state of the bus can be ascertained by reading the contents of SBISR.
SBISR will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
SCL pin
Start condition
A6
Slave address and the direction bit
Acknowledge
signal
1
SDA pin
2 3 4 5 6 7 8 9
A5 A4 A3 A2 A1 A0 R/ W
Stop condition
SCL pin
SDA pin