Zilog Z80230 - Manual (Page 9)

SCC/ESCC
User Manual
UM010903-0515 General Description
2
NMOS:
Description applies to NMOS version (Z8030/Z8530)
CMOS:
Description applies to CMOS version (Z80C30/Z85C30)
ESCC:
Description applies to ESCC (Z80230/Z85230/Z8523L)
EMSCC:
Description applies to EMSCC (Z85233)
Z80X30:
Description applies to Z-Bus version of the device (Z8030/Z80C30/Z80230)
Z85X3X:
Description applies to Universal version of the device (Z8530/Z85C30/Z85230/
Z8523L/Z85233)
The Z-Bus version has a multiplexed bus interface and is directly compatible with the Z8000,
Z16C00, and 80x86 CPUs. The Universal version has a non-multiplexed bus interface and easily
interfaces with virtually any CPU, including the 8080, Z80 ® , 68X00.
SCC’s Capabilities
The NMOS version of the SCC is Zilog’s original device. The design is based on the Z80 SIO
architecture. If you are familiar with the Z80 SIO, the SCC can be treated as an SIO with support
circuitry such as DPLL, BRG, etc. Its features include:
• Two independent full-duplex channels
• Synchronous/Isosynchronous data rates:
– Up to 1/4 of the PCLK using external clock source
– Up to 5 Mbits/sec at 20 MHz PCLK (ESCC)
– Up to 4 Mbits/sec at 16 MHz PCLK (CMOS)
– Up to 2 Mbits/sec at 8 MHz PCLK (NMOS)
– Up to 1/8 of the PCLK (up to 1/16 on NMOS) using FM encoding with DPLL
– Up to 1/16 of the PCLK (up to 1/32 on NMOS) using NRZI encoding with DPLL
• Asynchronous Capabilities
– 5, 6, 7 or 8 bits/character (capable of handling 4 bits/character or less.)
– 1, 1.5, or 2 stop bits
– Odd or even parity
– Times 1, 16, 32 or 64 clock modes
– Break generation and detection
– Parity, overrun and framing error detection
• Byte oriented synchronous capabilities:
– Internal or external character synchronization
– One or two sync characters (6 or 8 bits/sync character) in separate registers