Zilog Z80230 - Manual (Page 263)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
256
The three LSBs of the PACs value specify the Ready/WAIT handling for the PCS3-PCS0 lines
which select the (E)SCC, ISCC, and (M)USC.
The three LSBs of the MPCS value specify the Ready/WAIT handling for the PCS4-PCS6 lines,
which select the IUSC. Both fields are shown here with the LSB’s 000, signifying that the 80186
should honor a WAIT on the external Ready/WAIT signal, but that it should not provide any mini-
mum wait.
Programming Mid-Range Memory to Reset ISCC, IUSC, and (M)USC
A Reset puts the ISCC, IUSC, and (M)USC in a state in which the first write to each device
implicitly goes to a Bus Configuration Register (BCR) that controls the device’s basic bus opera-
tion. The BCR is not accessible thereafter.
This board can serve as a complete development environment for your software. It includes a
means where software (that is, the debug monitor) can assert the RESET input of these three
devices. Specifically, assertion of the MCS2 output of the 80186 such a Reset.
Table lists suggested MMCS values as a function of the RAM chip size, and the corresponding
range of addresses for which any read or write access causes the three controllers to be reset
.
The three LSBs of the above MMCS values are 111 so that the longest possible Reset pulse is gen-
erated when any of the locations in the indicated range are accessed.
If this feature is not required, it can be disabled by not programming the MMCS register.
Three Standard Alternatives for Serial Controller Addressing
Basic Requirement Base Address (BPA) PACS Value MPCS Value
I/O Space 8000 0838 81B8
Memory Space, 32K x 8 SRAMs
Used
38000 3838 81F8
Memory Space, 128K x 8 SRAMs
Used
D8000 D838 81F8
Address Ranges for Reset
RAM Size MMCS Value Address Range for which ISCC, IUSC, and (M)USC are Reset
32K x 8 3BFF
3B000-3B7FF
128K x 8 DBFF
DB000-DB7FF
Note: