Zilog Z80230 - Manual (Page 22)

SCC/ESCC
User Manual
UM010903-0515 General Description
15
clock, the clock for the baud rate generator, or the clock for the Digital Phase-Locked Loop. These
pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. With the crystal
oscillator option selected, these /RTxCA, /RTxCB pins become the oscillator Xin pins and
/SYNCA, /SYNCB pins become the Xout pins, respectively.
TxDA, TxDB.
Transmit Data (outputs, active High). These output signals transmit serial data at
standard TTL levels.
/TRxCA, /TRxCB.
Transmit/Receive Clocks (inputs or outputs, active Low). These pins can be
programmed in several different modes of operation. /TRxC may supply the receive clock or the
transmit clock in the input mode or supply the output of the Transmit Clock Counter (which paral-
lels the Digital Phase-Locked Loop), the crystal oscillator, the baud rate generator, or the transmit
clock in the output mode.
PCLK.
Clock (input). This is the master SCC clock used to synchronize internal signals. PCLK is
a TTL level signal. PCLK is not required to have any phase relationship with the master system
clock.
IEI.
Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt daisy chain
when there is more than one interrupt driven device. A high IEI indicates that no other higher pri-
ority device has an interrupt under service or is requesting an interrupt.
IEO.
Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is
not servicing the SCC interrupt or the SCC is not requesting an interrupt (Interrupt Acknowledge
cycle only). IEO is connected to the next lower priority device’s IEI input and thus inhibits inter-
rupts from lower priority devices.
/INT.
Interrupt (output, open drain, active Low). This signal is activated when the SCC requests an
interrupt. Note that /INT is an open-drain output.
/INTACK.
Interrupt Acknowledge (input, active Low). This is a strobe which indicates that an
interrupt acknowledge cycle is in progress. During this cycle, the SCC interrupt daisy chain is
resolved. The device is capable of returning an interrupt vector that may be encoded with the type
of interrupt pending. During the acknowledge cycle, if IEI is high, the SCC places the interrupt
vector on the databus when /RD goes active. /INTACK is latched by the rising edge of PCLK.
Pin Descriptions, (Z85X30 Only)
D7-D0.
Data bus (bidirectional, tri-state). These lines carry data and commands to and from the
Z85X30.
/CE.
Chip Enable (input, active Low). This signal selects the Z85X30 for a read or write opera-
tion.
/RD.
Read (input, active Low). This signal indicates a read operation and when the Z85X30 is
selected, enables the Z85X30’s bus drivers. During the Interrupt Acknowledge cycle, /RD gates
the interrupt vector onto the bus if the Z85X30 is the highest priority device requesting an inter-
rupt.