Zilog Z80230 - Manual (Page 189)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
182
Read Register 4 (ESCC and 85C30 Only)
On the ESCC, Read Register 4 reflects the contents of Write Register 4 provided the Extended
Read option is enabled. Otherwise, this register returns an image of RR0.
On the NMOS/CMOS version, a read to this location returns an image of RR0.
Read Register 5 (ESCC and 85C30 Only)
On the ESCC, Read Register 5 reflects the contents of Write Register 5 provided the Extended
Read option is enabled. Otherwise, this register returns an image of RR1.
On the NMOS/CMOS version, a read to this register returns an image of RR1.
Read Register 6 (Not on NMOS)
On the CMOS and ESCC, Read Register 6 contains the least significant byte of the frame byte
count that is currently at the top of the Status FIFO. RR6 is displayed in Figure on page 183. This
register is readable only if the FIFO is enabled (refer to the description Write Register 15, bit D2,
and SDLC Frame Status FIFO on page 126). Otherwise, this register is an image of RR2.
On the NMOS version, a read to this register location returns an image of RR2.
Read Register 7 (Not on NMOS)
On the CMOS and ESCC, Read Register 7 contains the most significant six bits of the frame byte
count that is currently at the top of the Status FIFO. Bit D7 is the FIFO Overflow Status and bit D6
is the FIFO Data Available Status. The status indications are given in Table on page 184. RR7 is
displayed in Figure on page 183. This register is readable only if the FIFO is enabled (refer to the
description Write Register 15, bit D2). Otherwise this register is an image of RR3. Note, for proper
operation of the FIFO and byte count logic, the registers should be read in the following order:
RR7, RR6, RR1.