Zilog Z80230 - Manual (Page 187)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
180
Bit 0: All Sent status
In Asynchronous mode, this bit is set when all characters have completely cleared the transmitter
pins. Most modems contain additional delays in the data path, which requires the modem control
signals to remain active until after the data has cleared both the transmitter and the modem. This
bit is always set in synchronous and SDLC modes.
Read Register 2
RR2 contains the interrupt vector written into WR2. When the register is accessed in Channel A,
the vector returned is the vector actually stored in WR2. When this register is accessed in Channel
B, the vector returned includes status information in bits 1, 2 and 3 or in bits 6, 5 and 4, depending
on the state of the Status High/Status Low bit in WR9 and independent of the state of the VIS bit
in WR9. The vector is modified according to Table on page 161 listed in the explanation of the
VIS bit in WR9 (See Write Register 8 (Transmit Buffer) on page 159). If no interrupts are pending,
the status is V3,V2,V1 -011, or V6,V5,V4-110. Figure on page 181 the bit positions for RR2.
1 0 1 0 7
0 1 1 0 8
1 1 1 1 8
0 0 0 2 8
Bits per Character Residue Decoding
Bits per Character Bit 3 Bit 2 Bit 1
8 0 1 1
7 0 0 0
6 0 1 0
5 0 0 1
I-Field Bit Selection (8 Bits Only) (Continued)
Bit 3 Bit 2 Bit 1
I-Field Bits in
Last Byte I-Field Bits in Previous Byte