Zilog Z80230 - Manual (Page 236)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
229
I/O Read Cycle
These tables show that a delay of the falling edge of /RD satisfies the SCC TsA(RD) timing
requirement of 50 ns min. The Z180 calculated value is 30 ns min for the worst case. Also, Z180
timing specification tAH (Address Hold time) is 10 ns min. The SCC timing parameters ThA(RD)
{Address to /RD High Hold} and ThCE(RD) {/CE to /RD High Hold} are minimum at 0 ns. The
rising edge of /RD is early to guarantee these parameters when considering address decoders and
gate propagation delays.
I/O Write Cycle
Delay the falling edge of /WR to satisfy the SCC TsA (/WR) timing requirement of 50 ns min. The
Z180 calculates 30 ns min worst case. Further, the Z180 timing specifications tAH (Address Hold
time) and tWDH (/WR High to data hold time) are both 10 ns min. The SCC timing parameters
ThA(WR) {Address to /WR High Hold}, ThCE(WR) {/CE to /WR High Hold} and TdWR(W)
{Write data to /WR High hold} are a minimum of 0 ns. The rising edge of /WR is early to guaran-
tee these parameter requirements.
Parameter Equations Worst Case (Without Delay Signals - No Wait State)
SCC
Parameters Z180 Equation Value (min) Units
TsA(RD) tcyc-tAD+tRDD1 30 ns
TdA(DR) 3tcyc+tCHW+tcf-tAD-tDRS 245 ns
TdRDf(DR) 2tcyc+tCHW+tcf-tRDD1-tDRS 160 ns
TwRDI 2tcyc+tCHW+tcf-tDRS+tRDD2 185 ns
TsA(WR) tcyc-tAD+tWRD1 30 ns
TsDW(WR) tWDS 15 ns
TwWRI tWRP 210 ns
Parameter Equations
Z180
Parameters SCC Equation Value (min) Units
tDRS Address
3tcyc+tCHW-tAD-TdA(DR)RD
241 ns
2tcyc+tCHW-tRDD1-TdRD(DR) 184 ns