Zilog Z80230 - Manual (Page 67)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
60
Block/DMA Transfer
The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and
DMA controllers. The Block Transfer mode uses the /W//REQ output in conjunction with the
Wait/Request bits in Write Register 1. The /W//REQ output can be defined by software as a /WAIT
line in the CPU Block Transfer mode or as a /REQ line in the DMA Block Transfer mode. The /
DTR//REQ pin can also be programmed through WR14 bit D2 to function as a DMA request for
the transmitter.
To a DMA controller, the SCC's /REQ outputs indicate that the SCC is ready to transfer data to or
from memory. To the CPU, the /WAIT output indicates that the SCC is not ready to transfer data,
thereby requesting the CPU to extend the I/O cycle.
Block Transfers
The SCC offers several alternatives for the block transfer of data. The various options are selected
by WR1 (bits D7 through D5) and WR14 (bit D2). Each channel in the SCC has two pins which
are used to control the block transfer of data. Both pins in each channel may be programmed to act
as DMA Request signals. The /W//REQ pin in each channel may be programmed to act as a Wait
signal for the CPU. In either mode, it is advisable to select and enable the mode in two separate
accesses of the appropriate register. The first access should select the mode and the second access
should enable the function. This procedure prevents glitches on the output pins. Reset forces Wait
mode, with /W//REQ open-drain.
Wait On Transmit
The Wait On Transmit function is selected by setting both D6 and D5 to 0 and then enabling the
function by setting D7 of WR1 to 1. In this mode the /W//REQ pin carries the /WAIT signal, and is
open-drain when inactive and Low when active. When the processor attempts to write to the trans-
mit buffer when it is full, the SCC asserts /WAIT until the byte is written (See Figure on page 61).