Zilog Z80230 - Manual (Page 165)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
158
Write Register 7 Prime (WR7')
Bit 7: Reserved.
This bit is reserved and must be programmed as 0.
Bit 6: Extended Read Enable bit
This bit enables the Extended Read. Setting this bit enables the reading of WR3, WR4, WR5,
WR7' and WR10. When this feature is enabled, these registers can be accessed by reading RR9,
RR4, RR5, RR14, and RR11, respectively. When this feature is not enabled, register access is to
the SCC. In this case, read to these register locations returns RR13, RR0, RR1, RR10, and RR15
respectively.
Bit 5: Receive Complete CRC
On this version, with this bit set to 1, the 2nd byte of the CRC is received completely. This feature
is ideal for applications which require a 2nd CRC byte for complete data; for example, a protocol
analyzer or applications using other than CRC-CCITT CRC (i.e., 32bit CRC).
In SDLC mode of operation, the CMOS SCC, on this bit is programmed as 0. In this case on the
EOF condition (when the closing flag is detected), the contents of the Receive Shift Register are
transferred to the Receive Data FIFO regardless of the number of bits assembled. Because of the
three-bit delay path between the sync register and the Receive Shift register, the last two bits of the
2nd byte of the CRC are never transferred to the Receive Data FIFO. The data is actually formed
with the six Least Significant Bits of the 2nd CRC byte.
Bit 4: /DTR//REQ Timing Fast Mode.
If this bit is set and the /DTR//REQ pin is used for Request Mode (WR14, bit D2=1), the deactiva-
tion of the /DTR//REQ pin is identical to the /W//REQ pin, which is triggered on the falling edge
of the /WR signal, and the /DTR//REQ pin goes inactive below 200 ns (this number varies
D7 D6 D5 D4 D3 D2 D1 D0
WR7' Prime
Auto Tx Flag
Auto EOM Reset
Auto/RTS Deactivation
Force TxD High
/DTR//REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)