Zilog Z80230 User Manual
Page 186
SCC/ESCC
User Manual
UM010903-0515
Register Descriptions
179
Bit 5: Receiver Overrun Error status
This bit indicates that the Receive FIFO has overflowed. Only the character that has been written
over is flagged with this error. When that character is read, the Error condition is latched until reset
by the Error Reset command.
Also, a Special Receive Condition vector is returned, caused by the overrun characters and all sub-
sequent characters received until the Error Reset command is issued.
On the CMOS and ESCC, if the Status FIFO is enabled (refer to the description in Write Register
15, bit D2 and the description in Read Register 7, bits D7 and D6), this bit reflects the status stored
at the exit location of the Status FIFO.
Bit 4: Parity Error status.
When parity is enabled, this bit is set for the characters whose parity does not match the pro-
grammed sense (even/odd). This bit is latched so that once an error occurs, it remains set until the
Error Reset command is issued. If the parity in Special Condition bit is set, a parity error causes a
Special Receive Condition vector to be returned on the character containing the error and on all
subsequent characters until the Error Reset command is issued.
Bits 3, 2, and 1: Residue Codes, bits 2, 1, and 0
In those cases in SDLC mode where the received I-Field is not an integral multiple of the character
length, these three bits indicate the length of the I-Field and are meaningful only for the transfer in
which the end of frame bit is set. This field is set to 011 by a channel or hardware reset and is
forced to this state in Asynchronous mode. These three bits can leave this state only if SDLC is
selected and a character is received. The codes signify the following (see
) when a receive
character length is eight bits per character.
On the CMOS and ESCC, if the Status FIFO is enabled (refer to the description in Write Register
15, bit D2 and the description in Read Register 7, bits D7 and D6), these bits reflect the status
stored at the exit location of the Status FIFO.
I-Field bits are right-justified in all cases. If a receive character length other than eight bits is used
for the I-Field, a table similar to
can be constructed for each different character length.
on page 180 lists the residue codes for no residue (The I-Field boundary lies on a character
boundary).
I-Field Bit Selection (8 Bits Only)
Bit 3 Bit 2
Bit 1
I-Field Bits in
Last Byte
I-Field Bits in Previous Byte
1
0
0
0
3
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6