Zilog Z80230 - Manual (Page 266)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
259
Then, the basic register map occurs twice in the even addresses from (PBA) through (PBA)+126
as listed in Table .
The redundant addressing of the (E)SCC is used to control a feature which can be used by soft-
ware to allow you to interrupt software execution from a keyboard. If the (E)SCC is read at an
address with
A6-A5=11
(for a multiplexed part, this means in the higher-addressed A Channel) a
mode is set in which a Low on the console Received Data line (Start bit on pin 3 of the J1 connec-
tor) causes a Non-Maskable Interrupt on the 80186. The mode is cleared by Reset or when the
(E)SCC is read at an address with A6-A5=10 (on a multiplexed part, in the higher addressees B
Channel). The NMI handler should do the latter to prevent subsequent data bits on the Received
Data line from causing further NMIs.
ISCC
Since 80186 processor provides multiplexed addresses and data, the ISCC is configured to use the
addresses on the AD lines. Software can address the various ISCC registers directly, and need not
be concerned with writing register addressees into the indirect address fields of the ISCC’s WR0
and CCAR.
As the ISCC includes four DMA channels, its Channel A and B Transmitters and Receivers can be
handled on a polled, interrupt-driven, and/or DMA basis, in any combination.
Since the ISCC can only be programmed as an 8-bit device on the AD7-AD0 lines, it occupies
only the even addressed bytes within its address range, [(PBA)+128 through (PBA)+190]. Details
of this transaction are as follows:
• The High induced by a pull-up resistor on the ISCC’s A/B input selects the WAIT protocol
on the WAIT/RDY pin, which corresponds to how the 80186 functions, in subsequent reg-
ister accesses, the AB selection is taken from A5 of the multiplexed address.
• A Low on the ISCC’s SCC/DMA input, which is connected to A6, is required by the inter-
nal logic of the ISCC. This is why the BCR write is restricted to the first half of the ISCC’s
address range.
• As with all transactions between 80186 and ISCC, the address must be even because the
ISCC only accepts slave-mode data on the AD7-AD0 pins.
Register Map
(PBA), (PBA)+2....(PBA)+30 Channel B Registers
0-15
(PBA)+32, +34.......(PBA)+62 Channel A Registers
0-15
(PBA)+64, +66.......(PBA)+94 Channel B Registers
0-15
(PBA)+96, +98.......(PBA)+126 Channel A Registers
0-15