Table – Zilog Z80230 User Manual
Page 30
SCC/ESCC
User Manual
UM010903-0515
Interfacing the SCC/ESCC
23
1
1
1
0
1
WR13A RR13A
RR13A
RR13A
1
1
1
1
0
WR14A RR14A
RR14A
(WR7’A)
1
1
1
1
1
WR15A RR15A
RR15A
RR15A
Notes
1. The register names in () are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7' bit D6 enables extend read function (only on ESCC).
4. Includes 80C30/230 when WR15 D2=0.
Z80X30 Register Map (Shift Right Mode)
READ 8030
80230
80C30/230* 80C30/230 WR15 D2=1
AD4 AD3 AD2 AD1 AD0 WRITE WR15 D2 = 0 WR15 D2=1 WR7’ D6 =1
0
0
0
0
0
WR0B RR0B
RR0B
RR0B
0
0
0
0
1
WR0A RR0A
RR0A
RR0A
0
0
0
1
0
WR1B RR1B
RR1B
RR1B
0
0
0
1
1
WR1A RR1A
RR1A
RR1A
0
0
1
0
0
WR2
RR2B
RR2B
RR2B
0
0
1
0
1
WR2
RR2A
RR2A
RR2A
0
0
1
1
0
WR3B RR3B
RR3B
RR3B
0
0
1
1
1
WR3A RR3A
RR3A
RR3A
0
1
0
0
0
WR4B (RR0B)
(RR0B)
(WR4B)
0
1
0
0
1
WR4A (RR0A)
(RR0A)
(WR4A)
0
1
0
1
0
WR5B (RR1B)
(RR1B)
(WR5B)
0
1
0
1
1
WR5A (RR1A)
(RR1A)
(WR5A)
0
1
1
0
0
WR6B (RR2B)
RR6B
RR6B
0
1
1
0
1
WR6A (RR2A)
RR6A
RR6A
Z80X30 Register Map (Shift Left Mode) (Continued)
READ 8030
80230
80C30/230* 80C30/230 WR15 D2=1
AD5 AD4 AD3 AD2 AD1 WRITE WR15 D2 = 0 WR15 D2=1 WR7' D6=1