Zilog Z80230 - Manual (Page 43)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
36
I/O Programming Introduction
The SCC can work with three basic forms of I/O operations: polling, interrupts, and block transfer.
All three I/O types involve register manipulation during initialization and data transfer. However,
the interrupt mode also incorporates Z-Bus interrupt protocol for a fast and efficient data transfer.
Regardless of the version of the SCC, all communication modes can use a choice of polling, inter-
rupt and block transfer. These modes are selected by the user to determine the proper hardware and
software required to supply data at the rate required.
Note to ESCC Users:
Those familiar with the NMOS/CMOS version will find the ESCC I/O
operations very similar but should note the following differences: the addition of software
acknowledge (which is available in the current version of the CMOS SCC, but not in NMOS); the
/DTR//REQ pin can be programmed to be deasserted faster; and the programmability of the data
interrupts to the FIFO fill level.
Polling
This is the simplest mode to implement. The software must poll the SCC to determine when data is
to be input or output from the SCC. In this mode, MIE (WR9, bit 3), and Wait/DMA Request
Enable (WR1, bit 7) are both reset to 0 to disable any interrupt or DMA requests. The software
must then poll RR0 to determine the status of the receive buffer, transmit buffer and external sta-
tus.
During a polling sequence, the status of Read Register 0 is examined in each channel. This register
indicates whether or not a receive or transmit data transfer is needed and whether or not any spe-
cial conditions are present, e.g., errors.
This method of I/O transfer avoids interrupts and, consequently, all interrupt functions should be
disabled. With no interrupts enabled, this mode of operation must initiate a read cycle of Read
Register 0 to detect an incoming character before jumping to a data handler routine.
Interrupts
Each of the SCC’s two channels contain three sources of interrupts, making a total of six interrupt
sources. These three sources of interrupts are: 1) Receiver, 2) Transmitter, and 3) External/Status
conditions. In addition, there are several conditions that may cause these interrupts. Figure on
page 37 displays the different conditions for each interrupt source and each is enabled under pro-
gram control. Channel A has a higher priority than Channel B with Receive, Transmit, and Exter-
nal/Status Interrupts prioritized, respectively, within each channel as listed in Table . The SCC
internally updates the interrupt status on every PCLK cycle in the Z85X30 and on /AS in the
Z80X30.
Interrupt Source Priority
Receive Channel A Highest
Transmit Channel A