Zilog Z80230 - Manual (Page 188)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
181
Read Register 2
Read Register 3
RR3 is the interrupt Pending register. The status of each of the interrupt Pending bits in the SCC is
reported in this register. This register exists only in Channel A. If this register is accessed in Chan-
nel B, all 0s are returned. The two unused bits are always returned as 0. Figure displays the bit
positions for RR3.
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 2
V0
V1
V2
V3
V4
V5
V6
V7
Interrupt
Vector
*
*
Modified In B Channel
D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3
Channel B Ext/Status IP
Channel B Tx IP
Channel B Rx IP
Channel A Ext/Status IP
Channel A Tx IP
Channel A Rx IP
0
0
*
*
Always 0 In B Channel