Zilog Z80230 - Manual (Page 269)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
262
While the ESCC and ISCC drive their Baud Rate Generators from their PCLK inputs, the (M)USC
has no such input. The 80186 clock output SYSCLK is brought to pins 7 of J9, J10, and J12, at
which point it can be jumpered to pin 9 or 8 so that it is routed to the TxC or RxC pin of the
device.
IUSC
Since the 80186 processor provides multiplexed addresses and data on the AD lines, the IUSC is 
configured to use these addresses. Software does not need to write register addresses into the indi-
rect address fields of the IUSC’s CCAR and DCAR.
The IUSC’s two DMA channels allow its Receiver and Transmitter to be handled on a polled,
interrupt-driven, or DMA basis, in any 
combination.
The IUSC can be programmed using 16-bit data on the AD15-AD0 lines or 8-bit data on AD15-
AD8 and AD7-AD0. The distinction between 8-bit and 16-bit operations is made as part of the
address map rather than via a control input.
The D/C pin of the IUSC is driven from A7 during slave cycles and the S/D pin is driven from
A8.The overall address range of the IUSC is 384 bytes from (PBA)+512 through (PBA)+895.
The first write to this address range, after a Reset, implicitly writes the IUSC’s Bus Configuration
Register (BCR). To match with the rest of the board’s hardware, this first write is a 16-bit write,
storing the recommended hex value
00F7
at any word address in the range (PBA)+768 through
(PBA)+830.
Details of this transaction are as follows:
• The High on the IUSC’s S/D input, which is connected to A8, selects the WAIT protocol
on the WAIT/RDY pin, which is how the 80186 works.
• It may not be required for this initial write, but it is good programming form to have A6
set to zero, since this is a word write. This and the first bullet determine the recommended
address range.
• The MSB of the data (D15) is 0 because a 
separate non-multiplexed address is not wired to Pins AD13:8 of the IUSC.
• Bits 14-8 are more or less required to be all 0’s by the IUSC’s internal logic.
(PBA)+448 (PBA)+511 8-bit access to (M)USC registers or USC Channel A Registers
Note: To maximize compatibility, program the (M)USC using the second half of this range (PBA)+384 through
(PBA)+511.
(M)USC Address Map
Starting Address Ending Address Registers Accessed