Zilog Z80230 - Manual (Page 38)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
31
There are three pointer bits in WR0, and these allow access to the registers with addresses 7
through 0. Note that a command may be written to WR0 at the same time that the pointer bits are
written. To access the registers with addresses 15 through 8, the Point High command must
accompany the pointer bits. This precludes concurrently issuing a command when pointing to
these registers.
The register map for the Z85X30 is listed in Table on page 31. If, for some reason, the state of the
pointer bits is unknown they may be reset to 0 by performing a read cycle with the D//C pin held
Low. Once the pointer bits have been set, the desired channel is selected by the state of the A//B
pin during the actual read or write of the desired register.
Z85X30 Register Map
Read 8530
85C30/230
85C30/230 WR15 D2=1
A//B PNT2 PNT1 PNT0 WRITE WR15 D2 = 0 WR15 D2=1 WR7' D6=1
0 0 0 0 WR0B RR0B RR0B RR0B
0 0 0 1 WR1B RR1B RR1B RR1B
0 0 1 0 WR2 RR2B RR2B RR2B
0 0 1 1 WR3B RR3B RR3B RR3B
0 1 0 0 WR4B (RR0B) (RR0B) (WR4B)
0 1 0 1 WR5B (RR1B) (RR1B) (WR5B)
0 1 1 0 WR6B (RR2B) RR6B RR6B
0 1 1 1 WR7B (RR3B) RR7B RR7B
1 0 0 0 WR0A RR0A RR0A RR0A
1 0 0 1 WR1A RR1A RR1A RR1A
1 0 1 0 WR2 RR2A RR2A RR2A
1 0 1 1 WR3A RR3A RR3A RR3A
1 1 0 0 WR4A (RR0A) (RR0A) (WR4A)
1 1 0 1 WR5A (RR1A) (RR1A) (WR5A)
1 1 1 0 WR6A (RR2A) RR6A RR6A
1 1 1 1 WR7A (RR3A) RR7A RR7A
With Point High Command
0
0 0 0 WR8B RR8B RR8B RR8B
0 0 0 1 WR9 (RR13B) (RR13B) (WR3B)