Zilog Z80230 - Manual (Page 10)

SCC/ESCC
User Manual
UM010903-0515 General Description
3
– Automatic Cyclic Redundancy Check (CRC) generation/detection
• SDLC/HDLC capabilities:
– Abort sequence generation and checking
– Automatic zero insertion and detection
– Automatic flag insertion between messages
– Address field recognition
– I-field residue handling
– CRC generation/detection
– SDLC loop mode with EOP recognition/loop entry and exit
• Receiver FIFO
ESCC: 8 bytes deep
NMOS/CMOS: 3 bytes deep
• Transmitter FIFO
ESCC: 4 bytes deep
NMOS/CMOS: 1 byte deep
• NRZ, NRZI or FM encoding/decoding. Manchester code decoding (encoding with exter-
nal logic)
• Baud Rate Generator in each channel
• Digital Phase Locked Loop (DPLL) for clock recovery
• Crystal oscillator
The CMOS version of the SCC is 100% plug in compatible to the NMOS versions of the device,
while providing the following additional features:
• Status FIFO
• Software interrupt acknowledge feature
• Enhanced timing specifications
• Faster system clock speed
• Designed in Zilog’s Superintegration™ core format
• When the DPLL clock source is external, it can be up to 2x the PCLK, where NMOS
allows up to PCLK (32.3 MHz max with 16/20 MHz version).
The Z85C30 CMOS SCC has added new features, while maintaining 100% hardware/software
compatibility. It has the following new features:
• New programmable WR7' (write register 7 prime) to enable new features.
• Improvements to support SDLC mode of synchronous communication: