Zilog Z80230 - Manual (Page 66)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
59
CTS/DCD
The CTS bit reports the state of the /CTS input, and the DCD bit reports the status of the /DCD
input. Both bits latch on either input transition. In both cases, after the Reset External/Status Inter-
rupt command is issued, if the latches are closed, they remain closed if there is any odd number of
transitions on an input; they open if there is an even number of transitions on the input.
Zero Count
The Zero Count bit is set when the counter in the baud rate generator reaches a count of 0 and is
reset when the counter is reloaded. The latches are closed only when this bit is set to 1. The status
in RR0 always reflects the current status. While the Zero count IE bit in WR15 is reset, this bit is
forced to 0.
Sync/Hunt
There are a variety of ways in which the Sync/Hunt may be set and reset, depending on the SCC’s
mode of operation. In the Asynchronous mode this bit reports the state of the /SYNC pin, latching
on both input transitions. The same is true of External Sync mode. However, if the crystal oscilla-
tor is enabled while in Asynchronous mode, this bit will be forced to 0 and the latches will not be
closed. Selecting the crystal option in External Sync mode is illegal, but the result will be the
same.
In Synchronous modes other than SDLC, the Sync/Hunt reports the Hunt state of the receiver.
Hunt mode is entered when the processor issues the Enter Hunt command in WR3. This forces the
receiver to search for a sync character match in the receive data stream. Because both transitions
of the Hunt bit close the latches, issuing this command will cause an External/Status interrupt. The
SCC resets this bit when character synchronization has been achieved, causing the latches to again
be closed.
In these synchronous modes, the SCC will not re-enter the Hunt mode automatically; only the
Enter Hunt command will set this bit. In SDLC mode this bit is also set by the Enter Hunt com-
mand, but the receiver automatically enters the Hunt mode if an Abort sequence is received. The
receiver leaves Hunt upon receipt of a flag sequence. Both transitions of the Hunt bit will cause
the latches to be closed. In SDLC mode, the receiver automatically synchronizes on Flag charac-
ters. The receiver is in Hunt mode when it is enabled, so the Enter Hunt command is never needed.
External/Status Interrupt Handling
If careful attention is paid to details, the interrupt service routine for External/Status interrupts is
straightforward. To determine which bit or bits changed state, the routine should first read RR0
and compare it to a copy from memory. For each changed bit, the appropriate action should be
taken and the copy in memory updated. The service routine should close with two Reset External/
Status interrupt commands to reopen the latches. The copy of RR0 in memory should always have
the Zero Count bit set to 0, since this is the state of the bit after the Reset External/Status interrupts
command at the end of the service routine. When the processor issues the Reset Transmit Under-
run/EOM latch command in WR0, the Transmit Underrun/EOM bit in the copy of RR0 in memory
should be reset because this transition does not cause an interrupt.