Zilog Z80230 - Manual (Page 181)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
174
mation read reflects the current status only. This bit is reset to 0 by a channel or hardware reset.
For details on this function, see SDLC Frame Status FIFO on page 126.
On the NMOS version, this bit is reserved and should be programmed as 0.
Bit 1: Zero Count Interrupt Enable
If this bit is set to 1, an External/Status interrupt is generated whenever the counter in the baud rate
generator reaches 0. This bit is reset to 0 by a channel or hardware reset.
Bit 0: Point to Write Register WR7 Prime (ESCC and 85C30 only)
When this bit is programmed to 0, writes to the WR7 address are made to WR7. When this bit is
programmed to 1, writes to the WR7 address are made to WR7 Prime. Once set, this bit remains
set unless cleared by writing a 0 to this bit or by a hardware or software reset. Note that if the
extended read option is enabled, WR7 Prime is read in RR14. For details about WR7', see ESCC
Enhancements for SDLC Transmit on page 118 and Write Register 7 Prime (ESCC only) on page
155.
On the NMOS/CMOS version, this bit is reserved and should be programmed as 0.
Read Registers
The SCC Read register set in each channel has four status registers (includes receive data FIFO),
and two baud rate time constant registers in each channel. The Interrupt Vector register (RR2) and
Interrupt Pending register (RR3) are shared by both channels. In addition to these, the CMOS/
ESCC has two additional registers for the SDLC Frame Status FIFO. On the ESCC, if that func-
tion is enabled (WR7' bit D6=1), five more registers are available which return the value written to
the write registers.
The status of these registers is continually changing and depends on the mode of communication,
received and transmitted data, and the manner in which this data is transferred to and from the
CPU. The following description details the bit assignment for each register.
Read Register 0 (Transmit/Receive Buffer Status and External Status)
Read Register 0 (RR0) contains the status of the receive and transmit buffers. RR0 also contains
the status bits for the six sources of External/Status interrupts. The bit configuration is displayed in
Figure on page 175.
On the NMOS/CMOS version, note that the status of this register might be changing during the
read.
An enhancement allows the ESCC and 85C30 to latch the contents of RR0 during read transac-
tions for this register. The latch is released on the rising edge of the /RD of the read transaction to