Interrupt control – Zilog Z80230 User Manual
Page 45
SCC/ESCC
User Manual
UM010903-0515
Interfacing the SCC/ESCC
38
D3. If WR7' D3=0, the receive character available interrupt is generated when one character is
loaded into the FIFO and is ready to be read. If WR7' D3=1, the receive character available
interrupt is generated when four bytes are available to be read in the receive data FIFO. The
programmed value of WR7' D5 also affects how DMA requests are generated. See
on page 60 for details.
If the ESCC is used in SDLC mode, it enables the SDLC Status FIFO to affect how
receive interrupts are generated. If this feature is used, read
on page 126 on the SDLC Anti-Lock Feature.
The special conditions are Receive FIFO overrun, CRC/framing error, end of frame, and
parity. If parity is included as a special condition, it is dependent on WR1 D2. The special
condition status can be read from RR1.
On the NMOS/CMOS versions, set the IP bit whenever the transmit buffer becomes
empty. This means that the transmit buffer was full before the transmit IP can be set.
ESCC:
The transmit interrupt request has only one source and is dependent on WR7' D5. If the IP bit
WR7' D5=0, it is set when the transmit buffer becomes completely empty. If IP bit WR7' D5=1,
the transmit interrupt is generated when the entry location of the FIFO is empty. Note that in
both cases the transmit interrupt is not set until after the first character is written to the ESCC.
For more information on Transmit Interrupts, see
Transmit Interrupts and Transmit Buffer Empty
on page 49 for details.
The External/status interrupts have several sources which may be individually enabled in WR15.
The sources are zero count, /DCD, Sync/Hunt, /CTS, transmitter under-run/EOM and Break/
Abort.
Interrupt Control
In addition to the MIE bit that enables or disables all SCC interrupts, each source of interrupt in
the SCC has three control/status bits associated with it. They are the Interrupt Enable (IE), Inter-
rupt Pending (IP), and Interrupt-Under-Service (IUS).
on page 39 displays the SCC inter-
rupt structure.
Note: