Zilog Z80230 - Manual (Page 230)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
223
Z180 to SCC Interface
The following subsections discuss the various parameters between the Z180/SCC interface:
• CPU hardware
• I/O operation (read/write)
• SCC interrupts
• Z80 interrupt daisy-chain operation
• SCC interrupt daisy-chain operation
• I/O cycles
CPU Hardware Interfacing
The hardware interface has three basic groups of signals:
1. Data bus
2. System control
3. Interrupt control.
For more detailed signal information, refer to Zilog’s Technical Manuals, and Product Specifica-
tions for each device.
Data Bus Signals
D7-D0:

Data bus (Bidirectional, tri-state). This bus transfers data between the Z180 and SCC.
System Control Signals
A//B, C//D:

Register select signals (Input). These lines select the registers.
/CE:

Chip enable (Input, active Low). /CE selects the proper peripheral for programming. /CE is gated
with /IORQ or /MREQ to prevent false chip selects during other machine cycles.
/RD+

Read (input, active Low). /RD activates the chip-read circuitry and gates data from the chip onto
the data bus.
/WR+

Write (Input, active Low). /WR strobes data from the data bus into the peripheral.
Chip reset occurs when /RD and /WR are active simultaneously.