Zilog Z80230 - Manual (Page 221)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
214
fetch cycle meet specifications, the design satisfies the timing requirements for a memory read
cycle.
Table has some equations for an opcode fetch, memory read/write cycle.
Parameter Equations (10 MHz) Opcode Fetch/Memory
Read/Write Cycle
The propagation delay for the decoded address and gates in the previous calculation is zero.
Hence, on the real design, subtracting another 20-30 ns to pay for propagation delays, is possible.
The 27C256 provides the EPROM for this board. Typical timing parameters for the 27C256 are in
Table .
EPROM (27C256) Key Timing Parameters (Values May Vary Depending On Mfg.)
Parameters Z180 Equation Value (min) Units
Address Valid to Data Valid
(Opcode Fetch)
2(1+w)tcyc-tAD-tDRS 105+100w ns
Address Valid to Data Valid
(Memory Read)
2(1+w)tcyc+tCHW+tcf-tAD-tDRS 155+100w ns
/MREQ Active to Data Valid
(Opcode Fetch)
(1+w)tcyc+tCLW-tMED1-tDRS 55+100w ns
/MREQ Active to Data Valid
(Memory Read)
(2+w)tcyc-tMED1-tDRS 105+100w ns
/RD Active to Data Valid
(Opcode Fetch)
(1+w)tcyc+tCLW-tRRD1-tDRS 55+100w ns
/RD Active to Data Valid
(Memory Read)
(2+w)tcyc-tRRD1-tDRS 105+100w ns
Memory Write Cycle /WR
Pulse Width
tWRP+w*tcyc 110+100w ns
Note: * w is the number of wait states.
Parameter
Access Time
170 ns 200 ns 250 ns
Max Max Max
Addr Access Time 170 200 250
/E to Data Valid 170 200 250