Zilog Z80230 - Manual (Page 140)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
133
SDLC Loop Mode Receive
SDLC Loop mode is quite similar to SDLC mode except that two additional control bits are used.
They are the Loop Mode bit (D1) and the Go-Active-On-Poll bit (D4) in WR10. In addition to
these two extra control bits, there are also two status bits in RR10. They are the On Loop bit (D1)
and the Loop Sending bit (D4).
Before Loop mode is selected, both the receiver and transmitter have to be completely initialized
for SDLC operation. Once this is done, Loop mode is selected by setting bit D1 of WR10 to 1. At
this point, the SCC connects TxD to RxD with only gate delays in the path. At the same time, a
flag is loaded into the Transmit Shift register and is shifted to the end of the zero inserter, ready for
transmission. The SCC remains in this state until the Go-Active-On-Poll bit (D4) in WR10 is set
to 1. When this bit is set to 1, the receiver begins looking for a sequence of seven consecutive 1s,
indicating either an EOP or an idle line. When the receiver detects this condition, the Break/Abort
bit in RR0 is set to 1, and a one-bit time delay is inserted in the path from RxD to TxD.
The On-Loop bit in RR10 is also set to 1 at this time, and the receiver enters the Hunt mode. The
SCC cannot transmit on the loop until a flag is received (causing the receiver to leave Hunt mode)
and another EOP (bit pattern 11111110) is received. The SCC is now on the loop and capable of
transmitting on the loop. As soon as this status is recognized by the processor, the Go-Active-On-
Poll bit in WR10 is set to 0 to prevent the SCC from transmitting on the loop without a processor
acknowledgment.
SDLC Loop Mode Transmit
To transmit a message on the loop, the Go-Active-On-Poll bit in WR10 must be set to 1. Once this
is done, the SCC changes the next received EOP into a Flag and begins transmitting on the loop.
When the EOP is received, the Break/Abort and Hunt bits in RR0 are set to 1, and the Loop Send-
ing bit in RR10 is also set to 1. Data to be transmitted is written after the Go-Active-On-Poll bit
has been set or after the receiver enters Hunt mode.
If the data is written immediately after the Go-Active-On-Poll bit has been set, the SCC only
inserts one flag after the EOP is changed into a flag. If the data is not written until after the
receiver enters the Hunt mode, the flags are transmitted until the data is written. If only one frame
is to be transmitted on the loop in response to an EOP, the processor must set the Go Active on
Poll bit to 0 before the last data is written to the transmitter. In this case, the transmitter closes the
frame with a single flag and then reverts to the one-bit delay.
The Loop Sending bit in RR10 is set to 0 when the closing Flag has been sent. If more than one
frame is to be transmitted, the Go-Active-On-Poll bit should not be set to 0 until the last frame is
being sent. If this bit is not set to 0 before the end of a frame, the transmitter sends Flags until
either more data is written to the transmitter, or until the Go-Active-On-Poll bit is set to 0. Note
that the state of the Abort/Flag on Underrun and Mark/Flag idle bits in WR10 is ignored by the
SCC in SDLC Loop mode.
SDLC Loop Initialization
The initialization sequence for the SCC in SDLC Loop mode is similar to the sequence used in
SDLC mode, except that it is longer. The processor should program WR4 first to select SDLC