Z80c30 register enhancement – Zilog Z80230 User Manual
Page 31
SCC/ESCC
User Manual
UM010903-0515
Interfacing the SCC/ESCC
24
Z80C30 Register Enhancement
The Z80C30 has an enhancement to the NMOS Z8030 register set, which is the addition of a
10x19 SDLC Frame Status FIFO. When WR15 bit D2=1, the SDLC Frame Status FIFO is
enabled, and it changes the functionality of RR6 and RR7. See Section
on page 126 for more details on this feature.
0
1
1
1
0
WR7B (RR3B)
RR7B
RR7B
0
1
1
1
1
WR7A (RR3A)
RR7A
RR7A
1
0
0
0
0
WR8B RR8B
RR8B
RR8B
1
0
0
0
1
WR8A RR8A
RR8A
RR8A
1
0
0
1
0
WR9
(RR13B)
(RR13B)
(WR3B)
1
0
0
1
1
WR9
(RR13A)
(RR13A)
(WR3A)
1
0
1
0
0
WR10B RR10B
RR10B
RR10B
1
0
1
0
1
WR10A RR10A
RR10A
RR10A
1
0
1
1
0
WR11B (RR15B)
(RR15B)
(WR10B)
1
0
1
1
1
WR11A (RR15A)
(RR15A)
(WR10A)
1
1
0
0
0
WR12B RR12B
RR12B
RR12B
1
1
0
0
1
WR12A RR12A
RR12A
RR12A
1
1
0
1
0
WR13B RR13B
RR13B
RR13B
1
1
0
1
1
WR13A RR13A
RR13A
RR13A
1
1
1
0
0
WR14B RR14B
RR14B
(WR7’B)
1
1
1
0
1
WR14A RR14A
RR14A
(WR7’A)
1
1
1
1
0
WR15B RR15B
RR15B
RR15B
1
1
1
1
1
WR15A RR15A
RR15A
RR15A
Notes
1. The register names in () are the values read out from that register location.
2. WR15 bit D2 enables status FIFO function (not available on NMOS).
3. WR7' bit D6 enables extend read function (only on ESCC).
4. * Includes 80C30/230 when WR15 D2=0.
Z80X30 Register Map (Shift Right Mode) (Continued)
READ 8030
80230
80C30/230* 80C30/230 WR15 D2=1
AD4 AD3 AD2 AD1 AD0 WRITE WR15 D2 = 0 WR15 D2=1 WR7’ D6 =1