Zilog Z80230 - Manual (Page 133)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
126
SDLC Frame Status FIFO
This feature is not available on the NMOS version.
On the CMOS version and the ESCC, the
ability to receive high speed back-to-back SDLC frames is maximized by a 10-bit deep by 19-bit
wide status FIFO. When enabled (through WR15, bit D2), it provides a DMA the ability to con-
tinue to transfer data into memory so that the CPU can examine the message later. For each SDLC
frame, a 14bit byte count and five status/error bits are stored. The byte count and status bits are
accessed through Read Registers 6 and 7. Read Registers 6 and 7 are only accessible when the
SDLC FIFO is enabled. The 10x19 status FIFO is separate from the 8-byte Receive Data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for the
SDLC frame is stored in the 10 x 19 bit status FIFO. This allows the DMA controller to transfer
the next frame into memory while the CPU verifies the message was properly received.
Summarizing the operation; data is received, assembled, and loaded into the eight-byte FIFO
before being transferred to memory by the DMA controller. When a flag is received at the end of
an SDLC frame, the frame byte count from the 14-bit counter and five status bits are loaded into
WR1
5
x x x x x x x 1 Enable access to new register
WR7
'
0 1 1 d 1 r 1 1 Enable extended read, Tx INT on FIFO
empty, d=REQUEST timing mode, Rx INT
on 4 char, r=RTS deactivation, auto EOM
reset, auto flag tx CRC preset to zero, NRZ
data,i=idle line
WR1
0
0 0 0 0 i 0 0 0 CRC preset to zero, NRZ data, i=idle line
WR3 r x 0 1 1 1 0 1 Enable Receiver
WR5 d t x 0 1 0 r 1 Enable Transmitter
WR0 1 0 0 0 0 0 0 0 Reset CRC generator
Notes
1. The receiver searches for synchronization when it is in Hunt mode. In this mode, the receiver
is idle except for searching the data stream for a flag match.
2. When the receiver detects a flag match it achieves synchronization and interprets the following
byte as the address field.
3. The SYNC/HUNT bit in RR0 reports the Hunt Status, and an interrupt is generated upon tran-
sitions between the Hunt state and the Sync state.
4. The SCC will drive the /SYNC pin Low for one receive clock cycle to signal that the flag has
been received.
Initializing in SDLC Mode
Bit#
Reg D7 D6 D5 D4 D3 D2 D1 D0 Description