Zilog Z80230 - Manual (Page 89)

SCC/ESCC
User Manual
UM010903-0515 SCC/ESCC Ancillary Support Circuitry
82
If no transition occurs between the middle of count 12 and the middle of count 19, the DPLL is
probably not locked onto the data properly. When the DPLL misses an edge, the One Clock Miss-
ing bit is RR10, it is set to 1 and latched. It will hold this value until a Reset Missing Clock com-
mand is issued in WR14, or until the DPLL is disabled or programmed to enter the Search mode.
Upon missing this one edge, the DPLL takes no other action and does not modify its count during
the next counting cycle.
If the DPLL does not see an edge between the middle of count 12 and the middle of count 19 in
two successive 0 to 31 count cycles, a line error condition is assumed. If this occurs, the Two
Clocks Missing bit in RR10 is set to 1 and latched. At the same time, the DPLL enters the Search
mode. The DPLL makes the decision to enter the Search mode during count 2, where both the
receive clock and transmit clock outputs are Low. This prevents any glitches on the clock outputs
when the Search mode is entered. While in the Search mode, no clock outputs are provided by the
DPLL. The Two Clocks Missing bit in RR10 is latched until a Reset Missing Clock command is
issued in WR14, or until the DPLL is disabled or programmed to enter the Search mode.
While the DPLL is disabled, the transmit clock output of the DPLL may be toggled by alternately
selecting FM and NRZI mode in the DPLL. The same is true of the receive clock.
While the DPLL is in the Search mode, the counter remains at count 16 where the receive output is
Low and the transmit output is Low. This fact is used to provide a transmit clock under software
control since the DPLL is in the Search mode while it is disabled.
As in NRZI mode, if an adjustment to the counting cycle is necessary, the DPLL modifies count 5,
either deleting it or doubling it. If no adjustment is necessary, the count sequence proceeds nor-
mally.
When the DPLL is programmed to enter Search mode, only clock transitions should exist on the
receive data pin. If this is not the case, the DPLL may attempt to lock on to the data transitions. If
the DPLL does lock on to the data transitions, then the Missing Clock condition will inevitably
occur because data transitions are not guaranteed every bit cell.
To lock in the DPLL properly, FM0 encoding requires continuous 1s received when leaving the
Search mode. In FM1 encoding, continuous 0s are required; with Manchester encoded data this
means alternating 1s and 0s. With all three of these data encoding methods there is always at least
one transition in every bit cell, and in FM mode the DPLL is designed to expect this transition.
DPLL Operation in the Manchester Mode
The SCC can be used to decode Manchester data by using the DPLL in the FM mode and pro-
gramming the receiver for NRZ data. Manchester encoded data contains a transition at the center
of every bit cell; it is the direction of this transition that distinguishes a 1 from a 0. Hence, for
Manchester data, the DPLL should be in FM mode (WR14 command D7=1, D6=1, D5=0), but the
receiver should be set up to accept NRZ data (WR10 D6=0, D5=0).