Zilog Z80230 - Manual (Page 128)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
121
The receiver automatically enters Hunt mode if an abort is received. Because the receiver always
searches the receive data stream for flags, and automatically enters Hunt Mode when an abort is
received, the receiver always handles frames correctly. The Enter Hunt Mode command should
never be needed. The SCC drives the /SYNC pin Low to signal that a flag has been recognized.
The timing for the /SYNC signal is displayed in Figure on page 121.
/SYNC as an Output
The SCC assumes the first byte in an SDLC frame is the address of the secondary station for which
the frame is intended. The SCC provides several options for handling this address.
If the Address Search Mode bit (D2) in WR3 is set to 0, the address recognition logic is disabled
and all received frames are transferred to the receive data FIFO. In this mode the software must
perform any address recognition.
If the Address Search Mode bit is set to 1, only those frames whose address matches the address
programmed in WR6 or the global address (all 1s) will be transferred to the receive data FIFO.
The address comparison is across all eight bits of WR6 if the Sync Character Load inhibit bit (D1)
in WR3 is set to 0. The comparison may be modified so that only the four most significant bits of
WR6 match the received address. This mode is selected by setting the Sync Character Load inhibit
bit to 1. In this mode, however, the address field is still eight bits wide. The address field is trans-
ferred to the receive data FIFO in the same manner as data. It is not treated differently than data.
The number of bits per character is controlled by bits D7 and D6 of WR3. Five, six, seven, or eight
bits per character may be selected via these two bits. The data is right-justified in the receive buf-
fer. The SCC merely takes a snapshot of the receive data stream at the appropriate times, so the
“unused” bits in the receive buffer are only the bits following the character.
State Changes in One
/RTxC Clock Cycle
/RTxC
PCLK
/SYNC