Zilog Z80230 - Manual (Page 164)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
157
If WR7' D3=1 and “Receive Interrupt on All Characters and Special Conditions” is enabled, the
Receive Character Available interrupt is triggered when the Rx FIFO is half full, i.e., the four byte
slots of the Rx FIFO are empty. However, if any character has a special condition, a special condi-
tion interrupt is generated when the character is loaded into the Receive FIFO. Therefore, the spe-
cial condition interrupt service routine should read RR1 before reading the data to determine
which byte has which special condition.
If WR7' D3=0, the ESCC sets the receiver and generates the receive character available interrupt
on every received character, regardless of any special receive condition.
Bit 2: Auto /RTS pin Deactivation
This bit controls the timing of the deassertion of the /RTS pin. If the ESCC is programmed for
SDLC mode and Flag-On-Underrun (WR10 D2=0), this bit is set and the RTS bit is reset. The /
RTS is deasserted automatically at the last bit of the closing flag, triggered by the rising edge of
the Transmit Clock. If this bit is reset, the /RTS pin follows the state programmed in WR5 D1.
Bit 1: Automatic EOM Reset
If this bit is set, the ESCC automatically resets the Tx Underrun/EOM latch and presets the trans-
mit CRC generator to its programmed preset state (per values set in WR5 D2 & WR10 D7).
Therefore, it is not necessary to issue the Reset Tx Underrun/EOM latch command when this fea-
ture is enabled. If this bit is reset, ESCC operation is identical to the SCC.
Bit 0: Automatic Tx SDLC Flag
If this bit is set, the ESCC automatically transmits an SDLC flag before transmitting data. This
removes the requirement to reset the mark idle bit (WR10 D3) before writing data to the transmit-
ter, or having to enable the transmitter before writing data to the Transmit FIFO. Also, this feature
enables a transmit data write before enabling the transmitter. If this bit is reset, operation is identi-
cal to that of the SCC.
Write Register 7 Prime (85C30 Only)
This Register is used only with the CMOS 85C30 SCC. WR7' is written to by first setting bit D0 of
WR15 to 1, and pointing to WR7 as normal. All writes to register 7 will be to WR7' so long as WR
D0 is set. WR 15 bit D0 must be reset to 0 to address the sync register, WR7. If bit D6 of WR7'
was set during the write, then WR7' can be read by accessing to RR14. The features remain
enabled until specifically disabled, or disabled by a hardware or software reset. Figure displays
WR7'.