Zilog Z80230 - Manual (Page 126)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
119
function is enabled in the ESCC to guarantee that the ESCC does not generate the edge before the
DMA is ready.
CRC takes priority over data:
On the NMOS/CMOS version, the data has higher priority over
CRC data. Writing data before the Tx interrupt, after loading the closing flag into the Transmit
Shift register, terminates the packet illegally. In this case, CRC byte(s) are replaced with Flag or
Sync patterns, followed by the data written. On the ESCC, CRC has priority over the data. Conse-
quently, after the Underrun/EOM (End of message) interrupt occurs, the ESCC accepts the data
for the next packet without fear of collapsing the packet. On the ESCC, if data was written during
the time period described above, the TBE bit (bit D2 of RR0) is NOT set; even if the 2nd TxIP is
guaranteed to set when the flag/sync pattern is loaded into the Transmit Shift register ( Transmit
Interrupts and Transmit Buffer Empty Bit on page 49). For the detailed timing on this, see Figure
on page 53 and Figure on page 53.
Hence, on the ESCC, there is no need to wait for the 2nd TxIP bit to set before writing data for the
next packet which reduces the overhead.
Auto EOM Reset (WR7' bit D1):
As described above, the Tx Underrun/EOM Latch has to be
reset before the Transmit Shift register completes shifting out the last character, but after first char-
acter has been written. One of the ways to reset it is for the CPU to issue the “Reset Tx Under-run/
EOM Latch” command. The other method to accomplish it is by the “Automatic EOM Latch
Reset feature” by setting bit D1 in WR7', which is one of the enhancements made to the ESCC. By
setting this bit to one, it eliminates the need for the CPU command. In this mode, the CRC genera-
tor is automatically reset at the start of every packet, without the CPU command. Hence, it is not
required to reset the CRC generator prior to writing data into the ESCC. This is particularly valu-
able to a DMA driven system where issuing CPU commands while the DMA is transferring data is
difficult. Also, it is very useful if the data rate is very high and the CPU may not be able to issue
the command on time.
Auto Tx Flag (WR7' bit D0):
With the NMOS/CMOS version of the SCC, in order to accomplish
Mark idle, it is required to enable the transmitter as Mark idle; then re-program to Flag idle before
writing first data, and then reprogram again to mark idle as described above. Normally, during
mark idle, the transmitter sends continuous flags, but the ESCC can idle MARK under program
control. By setting the Mark/Flag idle bit (D3) in WR10 to 1, the transmitter sends continuous 1s
in place of the idle flags. The closing flag always transmits correctly even when this mode is
selected. Normally, it is necessary to reset WR10 D3 to 0 before writing data for the next frame.
However, on the ESCC, if WR7' bit D0 is set to 1, an opening flag is transmitted automatically and
it is not necessary for the CPU to turn the Mark Idle feature on and off between frames.
When this mode in not in effect (WR7' D0=0), the Mark/Flag idle bit is clear to 0, allowing
a flag to be transmitted before data is written to the transmit buffer. Care must be exercised
in doing this because the continuous 1s are transmitted eight at a time and all eight must
leave the Transmit Shift register. This allows a flag to be loaded into it before the first data
is written to the Transmit FIFO.
Auto RTS Deactivation (WR7' bit D2):
Some applications require toggling the modem signal to
indicate the end of the packet. With the NMOS/CMOS version, this requires intensive CPU sup-
Note: