Zilog Z80230 - Manual (Page 109)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
102
The SCC does not automatically preset the CRC generator in byte Synchronous modes, so this
must be done in software. This is accomplished by issuing the Reset Tx CRC Generator command,
which is encoded in bits D7 and D6 of WR0. For proper results, this command is issued while the
transmitter is enabled and sending sync characters.
If the CRC is to be used, the transmit CRC generator must be enabled by setting bit D0 of WR5 to
1. This bit may also be used to exclude certain characters from the CRC calculation. Sync charac-
ters (from sync registers) are automatically excluded from the CRC calculation, and any characters
written as data are excluded from the calculation by using bit D0 of WR5. Internally, enabling or
disabling the CRC for a particular character happens at the same time the character is loaded from
the transmit data buffer (on the ESCC, the Transmit FIFO) to the Transmit Shift register. Thus, to
exclude a character from the CRC calculation bit, D0 of WR5 is set to 0 before the character is
written to the transmit buffer (on the ESCC, the Transmit FIFO).
ESCC:
Since the ESCC has a four-byte FIFO, if a character is to be excluded from the CRC calcula-
tion, it is recommended that only one byte be written to the ESCC at that time. If WR7' D5 is
reset, the transmit interrupt is generated when the FIFO is completely empty. This can be used
as a signal to reset WR5 bit D0, and then the character can be written to the Transmit FIFO.
This guarantees that the internal disable occurs when the character moves from the buffer to
the shift register. Once the buffer becomes empty, the Tx CRC Enable. The initialization
sequence for the transmitter in character bit is written for the next character.
Enabling the CRC generator is not sufficient to control the transmission of the CRC. In the SCC,
this function is controlled by the Tx Underrun/EOM bit, which is reset by the processor and set by
the SCC. When the transmitter underruns (both the transmit buffer and Transmit Shift register are
empty) the state of the Tx Underrun/EOM bit determines the action taken by the SCC. If the Tx
Underrun/EOM bit is reset when the underrun occurs, the transmitter sends the accumulated CRC
and sets the Tx Underrun/EOM bit to indicate this. This transition is programmed to cause an
external/status interrupt, or the Tx Underrun/EOM is available in RR0.
The Reset Tx Underrun/EOM Latch command is encoded in bits D7 and D6 of WR0. For correct
transmission of the CRC at the end of a block of data, this command is issued after the first charac-
ter is written to the SCC but before the but before the transmitter underruns. The command is usu-
ally issued immediately after the first character is written to the SCC so that the CRC is sent if an
underrun occurs inadvertently during the block of data.
85X30
If WR7' bit D1 is set, the Reset Transmit Underrun/EOM latch is automatically reset after the first
byte is written to the transmitter. This eliminates the need for the CPU to issue this command. This
feature can be particularly useful to applications using a DMA to write data to the transmitter since
there is no longer a need to interrupt the data transfers to issue this command.
If the transmitter is disabled during the transmission of a character, that character is sent com-
pletely. This applies to both data and sync characters. However, if the transmitter is disabled dur-