Zilog Z80230 - Manual (Page 143)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
136
Register Descriptions
Introduction
This section describes the functions of the various bits in the registers of the SCC (See Table and
Table on page 137). Reserved bits are not used in this implementation of the device and may or
may not be physically present in the device. For the register addresses, also see Table on page 21,
Table on page 23, and Table on page 31. Reserved bits that are physically present are readable
and writable but reserved bits that are not present will always be read as zero. To ensure compati-
bility with future versions of the device, reserved bits should always be written with zeros.
Reserved commands are not used for the same reason.
SCC Write Registers
Reg Description
WR0 Reg. pointers, various initialization commands
WR1 Transmit and Receive interrupt enables, WAIT/DMA
commands
WR2 Interrupt Vector
WR3 2 Receive parameters and control modes
WR4 2 Transmit and Receive modes and parameters
WR5 2 Transmit parameters and control modes
WR6 Sync Character or SDLC address
WR7 Sync Character or SDLC flag
WR7' 1 Extended Feature and FIFO Control (WR7 Prime)
WR8 Transmit buffer
WR9 Master Interrupt control and reset commands
WR10 2 Miscellaneous transmit and receive control bits
WR11 Clock mode controls for receive and transmit
WR12 Lower byte of baud rate generator
WR13 Upper byte of baud rate generator
WR14 Miscellaneous control bits