Zilog Z80230 - Manual (Page 74)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
67
If WR7' D4=1, analysis should be done to verify that the ESCC is not repeatedly accessed
in less than four PCLKs. However, since many DMAs require four clock cycles to transfer
data, this typically is not a problem.
In the Request mode, /REQ will follow the state of the transmit buffer even though the transmitter
is disabled. Thus, if /REQ is enabled before the transmitter is enabled, the DMA may write data to
the SCC before the transmitter is enabled. This does not cause a problem in Asynchronous mode,
but may cause problems in Synchronous modes because the SCC sends data in preference to flags
or sync characters. It may also complicate the CRC initialization, which cannot be done until after
the transmitter is enabled. On the ESCC, this complication can be avoided in SDLC mode by
using the Automatic SDLC Opening Flag Transmission feature and Auto EOM reset feature which
also resets the transmit CRC. (See ESCC Enhancements for SDLC Transmit on page 118 for
details). Applications using other synchronous modes should enable the transmitter before
enabling the /REQ function.
With only one exception, the /REQ pin directly follows the state of the Transmit FIFO (for ESCC,
as programmed by WR7' D5) in this mode. The one exception occurs in synchronous modes at the
end of a CRC transmission. At the end of a CRC transmission, when the closing flag or sync char-
acter is loaded into the Transmit Shift Register, /REQ is pulsed High for one PCLK cycle. The
DMA uses this falling edge on /REQ to write the first character of the next frame to the SCC.
DMA Request On Receive
The Request On Receive function is selected by setting D6 and D5 of WR1 to 1 and then enabling
the function by setting D7 of WR1 to 1. In this mode, the /W//REQ pin carries the /REQ signal,
which is active Low. When REQ on Receive is selected, but not yet enabled (WR1 D7=0), the /W/
/REQ pin is driven High. When the enable bit is set, /REQ goes Low if the Receive FIFO contains
a character at the time, or will remain High until a character enters the Receive FIFO. Note that the
/REQ pin follows the state of the Receive FIFO even though the receiver is disabled. Thus, if the
receiver is disabled and /REQ is still enabled, the DMA transfers the previously received data cor-
rectly. In this mode, the /REQ pin directly follows the state of the Receive FIFO with only one
exception. /REQ goes Low when a character enters the Receive FIFO and remains Low until this
character is removed from the Receive FIFO.
The SCC generates only one falling edge on /REQ per character transfer requested (See Figure on
page 68). The one exception occurs in the case of a special receive condition in the Receive Inter-
rupt on First Character or Special Condition mode, or the Receive Interrupt on Special Condition
Only mode. In these two interrupt modes, any receive character with a special receive condition is
locked at the top of the FIFO until an Error Reset command is issued. This character in the
Receive FIFO would ordinarily cause additional DMA Requests after the first time it is read.
However, the logic in the SCC guarantees only one falling edge on /REQ by holding /REQ High
Note: