Zilog Z80230 - Manual (Page 28)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
21
If there is an interrupt pending in the SCC, and IEI is High when /DS falls, the acknowl-
edge cycle was intended for the SCC. This being the case, the Z80X30 sets the Interrupt-Under-
Service (IUS) latch for the highest priority pending interrupt, as well as placing an interrupt vector
on AD7-AD0. The placing of a vector on the bus can be disabled by setting WR9, D1=1. The /INT
pin also goes inactive in response to the falling edge of /DS. Note that there should be only one /
DS per acknowledge cycle. Another important fact is that the IP bits in the Z80X30 are updated by
/AS, which may delay interrupt requests if the processor does not supply /AS strobes during the
time between accesses of the Z80X30.
Z80X30 Register Access
The registers in the Z80X30 are addressed via the address on AD7-AD0 and are latched by the ris-
ing edge of /AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are
decoded to form the register address. It is placed in this register to simplify programming when the
current state of the Shift Right/Shift Left bit is not known.
A hardware reset forces Shift Left mode where the address is decoded from AD5-AD1. In Shift
Right mode, the address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via a
command to make the software writing to WR0 independent of the state of the Shift Right/Shift
Left bit.
While in the Shift Left mode, the register address is placed on AD4-AD1 and the Channel Select
bit, A/B, is decoded from AD5. The register map for this case is listed in Table on page 21. In
Shift Right mode, the register address is again placed on AD4-AD1 but the channel select A/B is
decoded from AD0. The register map for this case is listed in Table on page 23.
Because the Z80X30 does not contain 16 read registers, the decoding of the read registers is not
complete; this is listed in Table on page 21 and Table on page 23 by parentheses around the reg-
ister name. These addresses may also be used to access the read registers. Also, note that the
Z80X30 contains only one WR2 and WR9; these registers may be written from either channel.
Shift Left Mode is used when Channel A and B are to be programmed differently. This allows the
software to sequence through the registers of one channel at a time. The Shift Right Mode is used
when the channels are programmed the same. By incrementing the address, the user can program
the same data value into both the Channel A and Channel B register.
Z80X30 Register Map (Shift Left Mode)
READ 8030 80230
80C30/230* 80C30/230 WR15 D2=1
AD5 AD4 AD3 AD2 AD1 WRITE WR15 D2 = 0 WR15 D2=1 WR7' D6=1
0
0 0 0 0 WR0B RR0B RR0B RR0B
0 0 0 0 1 WR1B RR1B RR1B RR1B