Zilog Z80230 - Manual (Page 78)

SCC/ESCC
User Manual
UM010903-0515 SCC/ESCC Ancillary Support Circuitry
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SCC/ESCC Ancillary Support Circuitry
Introduction
The serial channels of the SCC are supported by ancillary circuitry for generating clocks and per-
forming data encoding and decoding. This chapter presents a description of these functional
blocks.
Note to ESCC/CMOS Users:
The maximum input frequency to the DPLL has been specified as
two times the PCLK frequency (Spec #16b TxRX(DPLL)). There are no changes to the baud rate
generators from the NMOS to the CMOS/ESCC.
Note to SCC Users:
The ancillary circuitry in the ESCC is the same as in the SCC with the fol-
lowing noted changes. The DPLL (Dual Phased-Locked Loop) output, when used as the transmit
clock source, has been changed to be free of jitter. Consequently, this only affects the use of the
DPLL as the transmit clock source (it is typically used for the receive clock source), this has no
effect on using the DPLL as the receive clock source.
Baud Rate Generator
The Baud Rate Generator (BRG) is essential for asynchronous communications. Each channel in
the SCC contains a programmable baud rate generator. Each generator consists of two 8-bit, time-
constant registers forming a16-bit time constant, a 16-bit down counter, and a flip-flop on the out-
put so that it outputs a square wave. On start-up, the flip-flop on the output is set High, so that it
starts in a known state, the value in the time-constant register is loaded into the counter, and the
counter begins counting down. When a count of zero is reached, the output of the baud rate gener-
ator toggles, the value in the time-constant register is loaded into the counter, and the process starts