Zilog Z80230 - Manual (Page 183)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
176
number of transitions on the /CTS pin causes another External/Status interrupt condition. If the
CTS IE bit is reset, it merely reports the current unlatched state of the /CTS pin.
Bit 4: Sync/Hunt status
The operation of this bit is similar to that of the CTS bit, except that the condition monitored by
the bit varies depending on the mode in which the SCC is operating.
When the XTAL oscillator option is selected in asynchronous modes, this bit is forced to 0 (no
External/Status interrupt is generated). Selecting the XTAL oscillator in synchronous or SDLC
modes has no effect on the operation of this bit.
The XTAL oscillator should not be selected in External Sync mode.
In Asynchronous mode, the operation of this bit is identical to that of the CTS status bit, except
that this bit reports the state of the /SYNC pin.
In External sync mode the /SYNC pin is used by external logic to signal character synchronization.
When the Enter Hunt Mode command is issued in External Sync mode, the /SYNC pin must be
held High by the external sync logic until character synchronization is achieved. A High on the /
SYNC pin holds the Sync/Hunt bit in the reset condition.
When external synchronization is achieved, /SYNC is driven Low on the second rising edge of the
Receive Clock after the last rising edge of the Receive Clock on which the last bit of the receive
character was received. Once /SYNC is forced Low, it is good practice to keep it Low until the
CPU informs the external sync logic that synchronization is lost or that a new message is about to
start. Both transitions on the /SYNC pin cause External/Status interrupts if the Sync/Hunt IE bit is
set to 1.
The Enter Hunt Mode command should be issued whenever character synchronization is lost. At
the same time, the CPU should inform the external logic that character synchronization has been
lost and that the SCC is waiting for /SYNC to become active.
In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to 1 by the
Enter Hunt Mode command. The Sync/Hunt bit is reset when the SCC established character syn-
chronization. Both transitions cause External/Status interrupts if the Sync/Hunt IE bit is set. When
the CPU detects the end of message or the loss of character synchronization, the Enter Hunt Mode
command should be issued to set the Sync/Hunt bit and cause an External/Status interrupt. In this
mode, the /SYNC pin is an output, which goes Low every time a sync pattern is detected in the
data stream.
In the SDLC modes, the Sync/Hunt bit is initially set by the Enter Hunt Mode command or when
the receiver is disabled. It is reset when the opening flag of the first frame is detected by the SCC.
An External/Status interrupt is also generated if the Sync/Hunt IE bit is set. Unlike the Monosync
and Bisync modes, once the Sync/Hunt bit is reset in SDLC mode, it does not need to be set when
the end of the frame is detected. The SCC automatically maintains synchronization. The only way
the Sync/Hunt bit is set again is by the Enter Hunt Mode command or by disabling the receiver.
Bit 3: Data Carrier Detect status