Asynchronous initialization, Byte-oriented synchronous mode – Zilog Z80230 User Manual
Page 105
SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
98
the state of WR7' D3. The RCA bit is set if there is at least one byte available, regardless of the
status of WR7' bit D3.
This is the initialization sequence for the receiver in Asynchronous mode. First, WR4 selects the
mode, then WR3 and WR5 select the various options. At this point, the other registers should be
initialized as necessary. When all of this is complete, the receiver may be enabled by setting bit D0
of WR3 to 1.
See
on page 45 for more details on receive interrupts.
Asynchronous Initialization
The initialization sequence for Asynchronous mode is listed in
. All of the SCC’s registers
should be re-initialized after a channel or hardware reset. Also, WR4 should be programmed first
after a reset.
At this point, the other registers should be initialized according to the hardware design such as
clocking, I/O mode, etc. When this is completed, the transmitter is enabled by setting WR5 bit D3
to 1 and the receiver is enabled by setting WR3 bit D0 to 1.
Byte-Oriented Synchronous Mode
The SCC supports three byte-oriented synchronous protocols. They are: monosynchronous, bisyn-
chronous, and external synchronous.
Initialization Sequence Asynchronous Mode
Reg
Bit No
Description
WR9
6, 7
Hardware or channel Reset
WR4
3, 2
Select Async Mode and the
number of stop bits*
0, 1
Select parity*
6, 7
Select clock mode*
WR3
7, 6
Select number of receive bits per
character
5
Select Auto Enables Mode*
WR5
6, 5
Select number of bits/char for
transmitter
1
Select modem control (RTS)
Note: * Initializes transmitter and receiver simultaneously.