Zilog Z80230 - Manual (Page 44)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
37
ESCC Interrupt Sources
ESCC:
The receive interrupt request is either caused by a receive character available or a special condi-
tion. When the receive character available interrupt is generated, it is dependent on WR7' bit
External/Status Channel A
Receive Channel B
Transmit Channel B
External/Status Channel B
Lowest
Interrupt Source Priority (Continued)
SCC
Interrupt
Receiver
Interrupt
Sources
Zero Count
Transmit Buffer Empty
Parity Error (If enabled)
End of Frame (SDLC)
Framing Error
Receive Overrun
DCD
SYNC/HUNT
CTS
Tx Underrun/EOM
Break/Abort
Transmitter
Interrupt
Source
External/Status
Interrupt
Sources
INT on all Rx Character
or Special Condition
Rx Interrupt on Special
Condition Only
INT on first Rx Character
or Special Condition
Receive Character Available