Zilog Z80230 - Manual (Page 241)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
234
The primary chip in this logic is the Shift register (HCT164), which generates /INTACK, /SCCRD
and /WAIT. During I/O and normal memory access cycles, the Shift Register (HCT164) remains
cleared because the /M1 signal is inactive during the opcode fetch cycle. Since the Shift Register
output is Low, control of /SCCRD and /WAIT is by other system logic and gated through the NOR
gate (HCT27). During I/O and normal memory access cycles, /SCCRD and /SCCWR are gener-
ated from the system /RD and /WR signals, respectively. The generation is by the logic at the top
of Figure
SCC Interrupt Acknowledge Cycle Timing
Normally, an Interrupt Acknowledge cycle appears from the Z180 during /M1 and /IORQ active
(which is detected on the third rising edge of PHI after T1). To get an early sign of an Interrupt
Acknowledge cycle, the Shift register decodes an active /M1. This is during the presence of an
inactive /MREQ on the rising edge of T2.
During an Interrupt Acknowledge cycle, the /INTACK signal is generated on the rising edge of
T2. Since it is the presence of /INTACK and an active SCCRD that gates the interrupt vector onto
the data bus, the logic also generates /SCCRD at the proper time. The timing parameter of concern
here is TdIAi(RD) [/INTACK to /RD (Acknowledge) Low delay]. This time delay allows the