Zilog Z80230 - Manual (Page 171)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
164
the first data byte is sent to the SCC, but before CRC has been transmitted. If the bit is not reset
before CRC is transmitted, extra flags are sent, slowing down response time on the loop. If this bit
is reset before the first data is written, the SCC completes the transmission of the present flag and
reverts to the 1-Bit Delay mode.
After gaining control of the loop, the SCC is not able to transmit again until a flag and another
EOP are received. It is good practice to set this bit only upon receipt of a poll frame to ensure that
the SCC does not go on-loop without the CPU noticing it.
In synchronous modes other than SDLC with the Loop Mode bit set, this bit is set before the trans-
mitter goes active in response to a received sync character.
This bit is always ignored in Asynchronous mode and Synchronous modes unless the Loop Mode
bit is set. This bit is reset by a channel or hardware reset.
Bit 3: Mark//Flag Idle line control bit
This bit affects only SDLC operation and is used to control the idle line condition. If this bit is set
to 0, the transmitter send flags as an idle line. If this bit is set to 1, the transmitter sends continuous
1s after the closing flag of a frame. The idle line condition is selected byte by byte i.e., either a flag
or eight 1s are transmitted. The primary station in an SDLC loop should be programmed for Mark
Idle to create the EOP sequence. Mark Idle must be deselected at the beginning of a frame before
the first data is written to the SCC, so that an opening flag is transmitted. This bit is ignored in
Loop mode, but the programmed value takes effect upon exiting the Loop mode. This bit is reset
by a channel or hardware reset.
On the ESCC and 85C30 with the Automatic TX SDLC Flag mode enabled (WR7', D0=1), this bit
can be left as mark idle. It will send an opening flag automatically, as well as sending a closing
flag followed by mark idle after the frame transmission is completed.
Bit 2: Abort//Flag On Underrun select bit
This bit affects only SDLC operation and is used to control how the SCC responds to a transmit
underrun condition. If this bit is set to 1 and a transmit underrun occurs, the SCC sends an abort
and a flag instead of a CRC. If this bit is reset, the SCC sends a CRC on a transmit underrun. At
the beginning of this 16-bit transmission, the Transmit Under-run/EOM bit is set, causing an
External/Status interrupt. The CPU uses this status, along with the byte count from memory or the
DMA, to determine whether the frame must be retransmitted.
To start the next frame, a Transmit Buffer Empty interrupt occurs at the end of this 16-bit transmis-
sion. If both this bit and the Mark/Flag Idle bit are set to 1, all 1s are transmitted after the transmit
underrun. This bit should be set after the first byte of data is sent to the SCC and reset immediately
after the last byte of data, terminating the frame properly with CRC and a flag. This bit is ignored
in Loop mode, but the programmed value is active upon exiting Loop mode. This bit is reset by a
channel or hardware reset.
Bit 1: Loop Mode control bit
In SDLC mode, the initial set condition of this bit forces the SCC to connect TxD to RxD and to
begin searching the incoming data stream so that it can go on loop. All bits pertinent to SDLC